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Ordering number : EN*5117
CMOS LSI
LC6529N, LC6529F, LC6529L
4-Bit Microcomputer for Small-Scale Control Applications
Preliminary Overview
The LC6529N/F/L provides the basic architecture and instruction set of the Sanyo LC6500 Series of 4-bit singlechip microcomputers in a version specially for small-scale control applications involving circuits built with standard logic elements, applications using simple, comparatorbased voltage or phase detectors, or other applications controlling a limited number of controls. The LC6529F is a replacement for the former LC6529H. (Certain functions differ, however.) The N (medium-speed) and L (powersaving) versions are new additions to the lineup. * Choice of clock oscillator options to match system specifications -- Oscillator circuit options: 2-pin RC oscillator circuit (N and L versions) or 2-pin ceramic oscillator circuit (N, F, and L versions) -- Frequency divider options: Built-in 1/3 and 1/4 frequency dividers that eliminate the need for external frequency dividers
Features
* Power-saving CMOS design (Standby mode accessed with HALT instruction included.) * Memory: 1 kilobyte of 8-bit ROM and 64 words of 4-bit RAM * Instruction set: 51-member subset of LC6500 standard complement of 80 instructions * (L version) Wide range of operating voltages: 2.2 to 6.0 V * (F version) 0.92 s/3.0 V instruction cycle time * Flexible I/O ports Four ports with up to 16 lines -- Bidirectional I/O ports: 12 Dedicated input ports: 4 (These double as comparator inputs.) -- I/O voltage limit: max. +15 V (open-drain configuration) -- Output current: max. 20 mA sink current (capable of directly driving an LED) Choice of options to match system specifications -- Choice of open-drain or pull-up resistor output configurations at the bit level for all ports -- Choice of reset output levels for Ports C and D in groups of 4 bits each Port E configurable as four comparator inputs * Stack: Four levels * Timers: 4-bit prescaler plus 8-bit programmable counter * Comparators: 4 channels (2 reference levels) Separator reference level for each channel pair -- Feedback resistor option for choice of input with or without hysteresis
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92995HA (OT) No. 5117-1/39
LC6529N, LC6529F, LC6529L Summary of Functions
Item [Memory] ROM RAM Instruction set [On-board functions] Timers Stack levels Standby mode Comparators [I/O ports] Number of ports I/O voltage limit Output current I/O circuit configuration Reset output level Port function [Characteristics] Minimum cycle time Operating temperature Power supply voltage Current drain [Clock] Oscillator Frequency divider options [Miscellaneous] Package OTP DIP24S, SSOP24, MFP30S Included DIP24S, SSOP24, MFP30S Included DIP24S, SSOP24, MFP30S Included RC (850 kHz, 400 kHz typ.) Ceramic oscillator (400 kHz, 800 kHz, Ceramic oscillator (2 MHz, 4 MHz) 2 MHz, 4 MHz) 1/1, 1/3, 1/4 1/1 RC (400 kHz typ.) Ceramic oscillator (400 kHz, 800 kHz, 2 MHz, 4 MHz) 1/1, 1/3, 1/4 2.77 s (VDD 3.0 V) -40 to +85C 3.0 to 6.0 V 1.1 mA typ. 0.92 s (VDD 3.0 V) -40 to +85C 3.0 to 6.0 V 1.6 mA typ. 3.84 s (VDD 2.2 V) -40 to +85C 2.2 to 6.0 V 1.0 mA typ. 12 bidirectional I/O pins, 4 input pins max. 15 V (ports A, C, and D) 10 mA typ. 20 mA max. 12 bidirectional I/O pins, 4 input pins max. 15 V (ports A, C, and D) 10 mA typ. 20 mA max. 12 bidirectional I/O pins, 4 input pins max. 15 V (ports A, C, and D) 10 mA typ. 20 mA max. 4-bit prescaler plus 8-bit programmable counter 4 HALT instruction places chip on standby. 4 channels (2 reference levels) 4-bit prescaler plus 8-bit programmable counter 4 HALT instruction places chip on standby. 4 channels (2 reference levels) 4-bit prescaler plus 8-bit programmable counter 4 HALT instruction places chip on standby. 4 channels (2 reference levels) 1024 x 8 bits 64 x 4 bits 51 1024 x 8 bits 64 x 4 bits 51 1024 x 8 bits 64 x 4 bits 51 LC6529N LC6529F LC6529L
Choice of open-drain output or pull-up resistors at the bit level for ports A, C, and D Choice of high or low in groups of 4 bits each (ports C and D) Port E configurable as four comparator inputs
Note: The oscillator constants will be announced once the recommended circuit design has been decided.
No. 5117-2/39
LC6529N, LC6529F, LC6529L Pin Assignments MFP30S
Package Dimensions
unit: mm 3073A-MFP30S
[LC6529N, 6529F, 6529L]
SANYO: MFP30S
unit: mm DIP24S/SSOP24 3067-DIP24S
[LC6529N, 6529F, 6529L]
SANYO: DIP24S
unit: mm 3175A-SSOP24
Note: Do not use dip-soldering when mounting the SSOP package on the circuit board.
[LC6529N, 6529F, 6529L]
SANYO: SSOP24
Note: The above diagrams give only the nominal dimensions. Contact Sanyo for drawings complete with tolerances.
No. 5117-3/39
LC6529N, LC6529F, LC6529L Pin Names OSC1, OSC2: TEST: RES: PA0 to PA3: PC0 to PC3: PD0 to PD3: PE0 to PE3: CMP0 to CMP3: VREF0, VREF1: Pins for RC or ceramic oscillator circuit Test pin Reset pin Bidirectional I/O port A, bits 0 to 3 Bidirectional I/O port C, bits 0 to 3 Bidirectional I/O port D, bits 0 to 3 Unidirectional input port E, bits 0 to 3 Comparator input port, bits 0 to 3 Reference inputs
System Block Diagram
RAM: AC: ALU: DP: E: OSC: TM: STS:
Data memory Accumulator Arithmetic and Logic Unit Data pointer E register Oscillator circuit Timer Status register
ROM: PC: IR: I.DEC: CF: ZF: TMF:
Program memory Program Counter Instruction Register Instruction Decoder Carry Flag Zero Flag Timer overflow Flag
No. 5117-4/39
LC6529N, LC6529F, LC6529L Pin Functions
Pin No. 1 1 Symbol VDD VSS I/O -- -- Function Power supply. Normally +5 V. Power supply. 0 V. Output driver type Options -- -- 1. 2-pin RC oscillator circuit (1-pin external clock) Pins for attaching external system clock oscillator circuit (RC or ceramic) 2. 2-pin ceramic oscillator circuit 3. Frequency divider options: 1/1, 1/3, 1/4 * Bidirectional I/O port A0 to A3: 4-bit * N channel: sink input (IP instruction), 4-bit output (OP current type instruction), 1-bit conditionals (BP * I/O voltage limit for and BNP instructions), 1-bit set and open-drain reset (SPB and RPB instructions) configuration: max. * PA3 also doubles as standby +15 V operation control. * P channel: high* Block chattering from entering PA3 impedance pull-up during the HALT instruction type execution cycle. * N channel: sink current type * I/O voltage limit for open-drain configuration: max. +15 V * P channel: lowimpedance pull-up type * N channel: sink current type PD0 4 PD1 PD2 PD3 I/O Bidirectional I/O port D0 to D3. Functions and options the same as PC0 to PC3. * I/O voltage limit for open-drain configuration: max. +15 V * P channel: highimpedance pull-up type * When configured for comparator input: CMP0 and CMP1 use reference voltage VREF0; CMP2 and CMP3 use reference voltage VREF1. * 4-bit (CMP0 to 3) input (IP instruction) * 1-bit conditionals (BP and BNP instructions) * When configured for port E input: I * 4-bit (E0-3) input (IP instruction) * 1-bit conditionals (BP and BNP instructions) * Comparator reference level inputs: CMP0 and CMP1 use reference voltage VREF0; CMP2 and CMP3 use reference voltage VREF1. * Connect to VSS when PE0/CMP0 to PE3/CMP3 configured as port E. * System reset input 1 RES I * Connect external capacitor for power up reset. * Low level input for a minimum of four clock cycles triggers a reset. 1 TEST I Chip test pin. Normally connect to VSS. State after reset -- --
1 1
OSC1 OSC2
I O
PA0 4 PA1 PA2 PA3 I/O
1. Open-drain output 2. Pull-up resistor * Choice of configuration 1. or 2. at bit level High output (output N channel transistor off)
1. Open-drain output 2. Pull-up resistor 3. High output after reset 4. Low output after reset * Choice of configuration 1. or 2. at bit level * Choice of configuration 3. or 4. at port (4-bit) level 1. Open-drain output 2. Pull-up resistor 3. High output after reset 4. Low output after reset * Choice of configuration 1. or 2. at bit level * Choice of configuration 3. or 4. at port (4-bit) level High or low (option) High or low (option)
PC0 4 PC1 PC2 PC3 I/O
* Bidirectional I/O port C0 to C3. Functions the same as PA0 to PA3 except that there is no the standby operation control. * Option controls whether output is high or low after reset.
1. Comparator input 2. Port E input 3. Without feedback resistor 4. With feedback resistor * Choice of configuration 1. or 2. at port (4-bit) level * Options 3. and 4. only available with 1.
4
PE0/CMP0 PE1/CMP1 PE2/CMP2 PE3/CMP3
I
4
2
VREF0 VREF1
I
No. 5117-5/39
LC6529N, LC6529F, LC6529L Oscillator Circuit Options
Name Circuit diagram Conditions, etc.
External clock
Leave OSC2 open.
2-pin RC oscillator circuit
2-pin ceramic oscillator circuit
Frequency Divider Options
Name Circuit diagram Conditions, etc.
No frequency divider (1/1)
Available with all three oscillator circuit options (N, F, and L versions)
1/3 frequency divider
Available only with external clock and ceramic oscillator circuit options (N and L versions)
1/4 frequency divider
Available only with external clock and ceramic oscillator circuit options (N and L versions)
Frequency Divider Options LC6529N
Oscillator circuit Frequency 400 kHz Frequency divider options (cycle time) 1/1 (10 s) 1/1 (5 s) 1/3 (15 s) 1/4 (20 s) 1/3 (6 s) 1/4 (8 s) 1/3 (3 s) 1/4 (4 s) 1/1 (20 to 2.77 s) 1/3 (20 to 2.77 s) 1/4 (20 to 3.70 s) VDD range 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 1/1 frequency divider option not available 1/1 frequency divider option not available Note 1/3 and 1/4 frequency divider options not available
800 kHz Ceramic oscillator 2 MHz 4 MHz External clock based on RC oscillator circuit 200 k to 1444 kHz 600 k to 4330 kHz 800 k to 4330 kHz
RC oscillator circuit
Use 1/1 frequency divider and recommended constants or, if this is not possible, one of the frequency, frequency divider option, and VDD range combinations listed for external clocks based on an RC oscillator circuit.
3 to 6 V
External clock based on ceramic oscillator circuit
This configuration not allowed. Use an external clock based on an RC oscillator circuit instead.
No. 5117-6/39
LC6529N, LC6529F, LC6529L LC6529F
Oscillator circuit Ceramic oscillator External clock based on RC oscillator circuit External clock based on ceramic oscillator circuit 4 MHz 200 k to 4330 kHz Frequency Frequency divider options (cycle time) 1/1 (1 s) 1/1 (20 to 0.92 s) VDD range 3 to 6 V 3 to 6 V Note
This configuration not allowed. Use an external clock based on an RC oscillator circuit instead.
LC6529L
Oscillator circuit Frequency 400 kHz Frequency divider options (cycle time) 1/1 (10 s) 1/1 (5 s) 1/3 (15 s) 1/4 (20 s) 1/3 (6 s) 1/4 (8 s) 1/4 (4 s) 1/1 (20 to 3.84 s) 1/3 (20 to 3.84 s) 1/4 (20 to 3.84 s) VDD range 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 1/1 frequency divider option not available 1/1 and 1/3 frequency divider options not available Note 1/3 and 1/4 frequency divider options not available
800 kHz Ceramic oscillator 2 MHz 4 MHz External clock based on RC oscillator circuit 200 k to 1040 kHz 600 k to 3120 kHz 800 k to 4160 kHz
RC oscillator circuit
Use 1/1 frequency divider and recommended constants or, if this is not possible, one of the frequency, frequency divider option, and VDD range combinations listed for external clocks based on an RC oscillator circuit.
2.2 to 6 V
External clock based on ceramic oscillator circuit
This configuration not allowed. Use an external clock based on an RC oscillator circuit instead.
Reset Level Options for Ports C and D The following two options are available for controlling the output levels of ports C and D in groups of four bits each.
Option High level output after reset Low level output after reset Conditions, etc. Selection affects all bits of port Selection affects all bits of port
Comparator vs. Port E Configuration Option The four pins PE0/CMP0 to PE3/CMP3 may be configured for comparator input or as port E.
Option Comparator input Port E input Conditions, etc. Selection affects all bits of port Selection affects all bits of port
No. 5117-7/39
LC6529N, LC6529F, LC6529L Comparator Options The comparators offer the following two configuration options.
Name Circuit diagram Conditions, etc.
Without feedback resistor
The comparator does not use hysteresis.
With feedback resistor
The comparator, in combination with an external resistor, uses hysteresis.
Port Output Configurations The bidirectional I/O ports A, C, and D offer a choice of two output configurations.
Name Circuit diagram Conditions, etc.
Open drain (OD)
With pull-up resistors (PU)
This option adds a high-impedance pull-up resistor for port A or D and a low-impedance one for port C.
No. 5117-8/39
LC6529N, LC6529F, LC6529L
Specifications
LC6529N Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VI1 Input voltage VI 2 VI3 Output voltage I/O voltages Peak output current VO VIO1 VIO2 IOP IOA Average output current IOA1 IOA2 Pd max1 Allowable power dissipation Pd max2 Pd max3 Operating temperature Storage temperature Topr Tstg VDD OSC1*1 TEST, RES Port E (PE) configuration OSC2 Open-drain (OD) configuration Pull-up (PU) resistor configuration PA, PC, PD PA, PC, PD: Average for pin over 100-ms interval PA: Total current for pins PA0 to PA3*2 PC, PD: Total current for pins PC0 to PC3 and PD0 to PD3*2 Ta = -40 to +85C (DIP24S) Ta = -40 to +85C (SSOP24) Ta = -40 to +85C (MFP30S) -40 -55 Conditions min -0.3 -0.3 -0.3 -0.3 typ max +7.0 VDD + 0.3 VDD + 0.3 VDD + 0.3 V V mA +15 VDD + 0.3 +20 +20 +40 +90 360 165 150 +85 +125 C mW mA V Unit V
Voltages up to that generated allowed. -0.3 -0.3 -2 -2 -6 -14
Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amplitude. 2. Averaged over 100-ms interval.
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter Supply voltage Standby voltage Symbol VDD VST VIH1 VIH2 VIH3 VIH4 VIH5 VIL1 VIL2 VIL3 VIL4 Input low level voltage VIL5 VIL6 VIL7 VIL8 VIL9 VIL10 Operating frequency (cycle time) fop (Tcyc) VDD VDD: Preserves contents of RAM and registers*. Open-drain (OD) configuration: With output N-channel transistor off Pull-up (PU) resistor configuration: With output N-channel transistor off PE: Using port E configuration RES: VDD = 1.8 to 6 V OSC1: Using external clock option PA, PC, PD: With output N-channel transistor off, VDD = 4 to 6 V PA, PC, PD: With output N-channel transistor off PE: Using port E configuration, VDD = 4 to 6 V PE: Using port E configuration OSC1: Using external clock option, VDD = 4 to 6 V OSC1: Using external clock option TEST: VDD = 4 to 6 V TEST RES: VDD = 4 to 6 V RES Using the built-in 1/3 or 1/4 frequency dividers extends the maximum to 4.33 MHz. Conditions min 3.0 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 200 (20) typ max 6.0 6.0 13.5 VDD VDD VDD VDD 0.3 VDD 0.25 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 1444 (2.77) kHz (s) V V Unit V V
Input high level voltage
Note: * Maintain the power supply voltage at VDD until the HALT instruction has completed execution, placing the chip in the standby mode. Block chattering from entering PA3 during the HALT instruction execution cycle.
Continued on next page. No. 5117-9/39
LC6529N, LC6529F, LC6529L
Continued from preceding page.
Parameter [External clock conditions] Frequency Pulse width Rise/fall times [Oscillator guaranteed constants] Cext 2-pin RC oscillator circuit Cext Rext Rext Ceramic oscillator OSC1, OSC2: VDD = 4 to 6 V, Figure 2 OSC1, OSC2: Figure 2 OSC1, OSC2: VDD = 4 to 6 V, Figure 2 OSC1, OSC2: Figure 2 Figure 3 See Table 1. 220 5% 220 5% 4.7 1% 12.0 1% pF text textH, textL OSC1: If the clock frequency exceeds 1.444 MHz, use the built-in 1/3 or 1/4 frequency divider. Figure 1 textR, textF 200 69 50 4330 kHz ns Symbol Conditions min typ max Unit
k
Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter Symbol IIH1 Input high level current IIH2 IIH3 IIL1 Conditions Open-drain (OD) configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = 13.5 V PE: Using port E configuration, VIN = VDD OSC1: Using external clock option, VIN = VDD Open-drain (OD) configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS Pull-up (PU) resistor configuration for port A or D: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS Pull-up (PU) resistor configuration for port C: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS PE: Using port E configuration, VIN = VSS RES: VIN = VSS OSC1: Using external clock option, VIN = VSS Pull-up (PU) resistor configuration for port C: IOH = -300 A, VDD = 4 to 6 V Pull-up (PU) resistor configuration for port C: IOH = -60 A PA, PC, PD: IOL = 10 mA, VDD = 4 to 6 V PA, PC, PD: With IOL for each port less than or equal to 1 mA, IOL = 1.8 mA RES OSC1*: Using RC oscillator or external clock option 0.1 VDD 0.1 VDD -1.0 A -220 -71.5 min typ max 5.0 1.0 1.0 A Unit
IIL2 Input low level current IIL3 IIL4 IIL5 IIL6 VOH1 Output high level voltage VOH2 VOL1 Output low level voltage VOL2 VHIS1 VHIS2
-6.00 -1.0 -45 -1.0 VDD - 1.2
-2.17
mA
-10
A
V VDD - 0.5 1.5 0.4 V
Hysteresis voltage
V
Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC1.
No. 5117-10/39
LC6529N, LC6529F, LC6529L
Parameter [Current drain] RC oscillator IDD OP1 IDD OP2 IDD OP3 IDD OP4 Ceramic oscillator IDD OP5 IDD OP6 IDD OP7 IDD OP8 IDD OP9 External clock IDD OP10 VDD: Figure 2, 850 kHz (typ) VDD: Figure 2, 400 kHz (typ) VDD: Figure 3, 4 MHz, 1/3 frequency divider VDD: Figure 3, 4 MHz, 1/4 frequency divider VDD: Figure 3, 2 MHz, 1/3 frequency divider VDD: Figure 3, 2 MHz, 1/4 frequency divider VDD: Figure 3, 800 kHz VDD: Figure 3, 400 kHz VDD: 200 to 667 kHz, 1/1 frequency divider, 600 to 2000 kHz, 1/3 frequency divider, 800 to 2667 kHz, 1/4 frequency divider VDD: 200 to 1444 kHz, 1/1 frequency divider, 600 to 4330 kHz, 1/3 frequency divider, 800 to 4330 kHz, 1/4 frequency divider VDD: With output N-channel transistor off and port level = VDD, VDD = 6 V VDD: With output N-channel transistor off and port level = VDD, VDD = 3 V OSC1, OSC2: Figure 2, Cext = 220 pF 5%, Rext = 12.0 k 1% OSC1, OSC2: Figure 2, Cext = 220 pF 5%, Rext = 4.7 k 1%, VDD = 4 to 6 V OSC1, OSC2: Figure 3, fO = 400 kHz Oscillator frequency fCFOSC* OSC1, OSC2: Figure 3, fO = 800 kHz OSC1, OSC2: Figure 3, fO = 2 MHz OSC1, OSC2: Figure 3, fO = 4 MHz Figure 4, fO = 400 kHz Oscillator stabilization interval [Pull-up resistors] RPP1 I/O ports RPP2 Reset port External reset characteristic: Reset time Pin capacitance Ru tRST CP f = 1 MHz, VIN = VSS for pins other than one being measured Pull-up (PU) resistor configuration for port A or D: With output N-channel transistor off and VIN = VSS, VDD = 5 V Pull-up (PU) resistor configuration for port C: With output N-channel transistor off and VIN = VSS, VDD = 5 V RES: VIN = VSS, VDD = 5 V 30 70 130 tCFS Figure 4, fO = 800 kHz, fO = 2 MHz, fO = 4 MHz, 1/3, 1/4 frequency divider 0.8 0.4 1.6 1.6 1.3 1.3 1.1 0.9 1.0 2.0 1.0 4.0 4.0 3.0 3.0 2.6 2.4 2.5 mA 1.6 4.2 mA mA Symbol Conditions min typ max Unit
IDD st1 Standby operation IDD st2 [Oscillator characteristics] (RC oscillator)
0.05 0.025
10 A 5
309 660
400 850
577 kHz 1229
Oscillator frequency
fMOSC
[Oscillator characteristics] (Ceramic oscillator) 384 768 1920 3840 400 800 2000 4000 416 832 2080 4160 10 10 ms kHz
1.0 200
2.3 500 See Figure 6.
3.9 725
k
10
pF
Note: * fCFOSC is the allowable oscillator frequency.
Comparator Characteristics for Comparator Option at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter Reference input voltage range Inphase input voltage range Offset voltage Response speed Symbol VRFIN VCMIN VOFF TRS1 TRS2 IIH1 IIH2 IIL1 IIL2 RCMFB VREF0 and VREF1 CMP0 to CMP3 VCMIN = VSS to VDD - 1.5 V Figure 5: VDD = 4 to 6 V Figure 5 VREF0 and VREF1 CMP0 to CMP3: Without feedback resistor option VREF0 and VREF1 CMP0 to CMP3: Without feedback resistor option CMP0 to CMP3: With feedback resistor option -1.0 -1.0 460 Conditions min VSS + 0.3 VSS 50 1.0 1.0 typ max VDD - 1.5 VDD - 1.5 300 5.0 200 1.0 1.0 Unit V V mV s
Input high level current
A
Input low level current Feedback resistor
A k
No. 5117-11/39
LC6529N, LC6529F, LC6529L Table 1 Guaranteed Constants for Ceramic Oscillators
Oscillator type [External capacitor] 4-MHz ceramic oscillator 2-MHz ceramic oscillator [Built-in capacitor] 4-MHz ceramic oscillator 2-MHz ceramic oscillator 800-kHz ceramic oscillator 400-kHz ceramic oscillator Murata Kyocera Murata Murata Kyocera Murata Kyocera CS A4.00MG KBR-4.0MSA CS A2.00MG CS B800J KBR-800F/Y CS B400P KBR-400BK/Y -- -- -- -- -- -- -- -- -- Kyocera -- Kyocera -- -- -- -- KBR-4.0MWS -- KBR-2.0MWS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Murata Kyocera Murata Kyocera CS A4.00MG KBR-4.0MSA CS A2.00MG KBR-2.0MSA 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% -- -- -- -- Murata -- Murata -- CS AC4.00MGC 33 pF 10% 33 pF 10% -- -- -- Standard type Manufacturer Oscillator C1 C2 Rd Manufacturer Chip type Oscillator C1 C2
CS AC2.00MGC 33 pF 10% 33 pF 10% -- -- --
100 pF 10% 100 pF 10% 3.3 k 150 pF 10% 150 pF 10% --
220 pF 10% 220 pF 10% 3.3 k 330 pF 10% 330 pF 10% --
Figure 1 External Clock Input Waveform
No. 5117-12/39
LC6529N, LC6529F, LC6529L
Figure 2 2-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
Figure 4 Oscillator Stabilization Interval
Figure 5 Comparator Response Speed (TRS) Timing
No. 5117-13/39
LC6529N, LC6529F, LC6529L
Note: When the power supply rising interval is zero, a value of 0.1 F for CRES produces a reset interval of 10 to 100 ms. If the power supply rising interval is larger, adjust CRES to produce a minimum interval of 10 ms for the oscillation to stabilize.
Figure 6 Reset Circuit LC6529N RC Oscillator Characteristics Figure 7 gives the RC oscillator characteristics for the LC6529N. The frequency fluctuation ranges are as follows: 1. For VDD = 3.0 to 6.0 V, Ta = -40 to +85C, Cext = 220 pF, and Rext = 12.0 k, 309 kHz fMOSC 577 kHz 2. For VDD = 4.0 to 6.0 V, Ta = -40 to +85C, Cext = 220 pF, and Rext = 4.7 k, 660 kHz fMOSC 1229 kHz These results are only guaranteed for the above RC constants. If the above values are not available, keep the RC constants within the following ranges. (See Figure 7.) Rext = 3 to 20 k, Cext = 150 to 390 pF Note: 1. The oscillator frequency must be within the range between 350 and 750 kHz for VDD = 5.0 V and Ta = 25C. 2. Make sure that the oscillator frequency remains well within the operating clock frequency range (See frequency divider option table.) for the two ranges VDD = 3.0 to 6.0 V, Ta = -40 to +85C and VDD = 4.0 to 6.0 V, Ta = -40 to +85C.
Figure 7 RC Oscillator Frequency Data (Sample Values)
No. 5117-14/39
LC6529N, LC6529F, LC6529L LC6529F Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VI1 Input voltage VI 2 VI3 Output voltage I/O voltages Peak output current VO VIO1 VIO2 IOP IOA Average output current IOA1 IOA2 Pd max1 Allowable power dissipation Pd max2 Pd max3 Operating temperature Storage temperature Topr Tstg VDD OSC1*1 TEST, RES Port E (PE) configuration OSC2 Open-drain (OD) configuration Pull-up (PU) resistor configuration PA, PC, PD PA, PC, PD: Average for pin over 100-ms interval PA: Total current for pins PA0 to PA3*2 PC, PD: Total current for pins PC0 to PC3 and PD0 to PD3*2 Ta = -40 to +85C (DIP24S) Ta = -40 to +85C (SSOP24) Ta = -40 to +85C (MFP30S) -40 -55 Conditions min -0.3 -0.3 -0.3 -0.3 typ max +7.0 VDD + 0.3 VDD + 0.3 VDD + 0.3 V V mA +15 VDD + 0.3 +20 +20 +40 +90 360 165 150 +85 +125 C mW mA V Unit V
Voltages up to that generated allowed. -0.3 -0.3 -2 -2 -6 -14
Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amplitude. 2. Averaged over 100-ms interval.
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter Supply voltage Standby voltage Symbol VDD VST VIH1 VIH2 VIH3 VIH4 VIH5 VIL1 VIL2 VIL3 VIL4 Input low level voltage VIL5 VIL6 VIL7 VIL8 VIL9 VIL10 Operating frequency (cycle time) [External clock conditions] Frequency Pulse width Rise/fall times Oscillator guaranteed constants Ceramic oscillator text textH, textL OSC1: Figure 1 textR, textF Figure 2 See Table 1. 200 69 50 4330 kHz ns fop (Tcyc) VDD VDD: Preserves contents of RAM and registers*. Open-drain (OD) configuration: With output N-channel transistor off Pull-up (PU) resistor configuration: With output N-channel transistor off PE: Using port E configuration RES: VDD = 1.8 to 6 V OSC1: Using external clock option PA, PC, PD: With output N-channel transistor off, VDD = 4 to 6 V PA, PC, PD: With output N-channel transistor off PE: Using port E configuration, VDD = 4 to 6 V PE: Using port E configuration OSC1: Using external clock option, VDD = 4 to 6 V OSC1: Using external clock option TEST: VDD = 4 to 6 V TEST RES: VDD = 4 to 6 V RES Conditions min 3.0 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 200 (20) typ max 6.0 6.0 13.5 VDD VDD VDD VDD 0.3 VDD 0.25 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 4330 (0.92) kHz (s) V V Unit V V
Input high level voltage
Note: * Maintain the power supply voltage at VDD until the HALT instruction has completed execution, placing the chip in the standby mode. Block chattering from entering PA3 during the HALT instruction execution cycle.
No. 5117-15/39
LC6529N, LC6529F, LC6529L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter Symbol IIH1 Input high level current IIH2 IIH3 IIL1 Conditions Open-drain (OD) configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = 13.5 V PE: Using port E configuration, VIN = VDD OSC1: Using external clock option, VIN = VDD Open-drain (OD) configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS Pull-up (PU) resistor configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS Pull-up (PU) resistor configuration for port C: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS PE: Using port E configuration, VIN = VSS RES: VIN = VSS OSC1: Using external clock option, VIN = VSS Pull-up (PU) resistor configuration for port C: IOH = -300 A, VDD = 4 to 6 V Pull-up (PU) resistor configuration for port C: IOH = -60 A PA, PC, PD: IOL = 10 mA, VDD = 4 to 6 V PA, PC, PD: With IOL for each port less than or equal to 1 mA, IOL = 1.8 mA RES OSC1*: Using RC oscillator or external clock option 0.1 VDD 0.1 VDD -1.0 A -220 -71.5 min typ max 5.0 1.0 1.0 A Unit
IIL2 Input low level current IIL3 IIL4 IIL5 IIL6 VOH1 Output high level voltage VOH2 VOL1 Output low level voltage VOL2 VHIS1 VHIS2
-6.00 -1.0 -45 -1.0 VDD - 1.2
-2.17
mA
-10
A
V VDD - 0.5 1.5 0.4 V
Hysteresis voltage
V
Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC1.
Parameter [Current drain] Ceramic oscillator External clock
Symbol
Conditions
min
typ
max
Unit
IDD OP1 IDD OP2 IDD st1
VDD: Figure 2, 4 MHz, 200 to 4330 kHz, 1/1 frequency divider Note: With output N-channel transistor off and port level = VDD VDD: With output N-channel transistor off and port level = VDD, VDD = 6 V VDD: With output N-channel transistor off and port level = VDD, VDD = 3 V OSC1, OSC2: Figure 2, fO = 4 MHz* Figure 3, fO = 4 MHz Pull-up (PU) resistor configuration for port A or D: With output N-channel transistor off and VIN = VSS, VDD = 5 V Pull-up (PU) resistor configuration for port C: With output N-channel transistor off and VIN = VSS, VDD = 5 V RES: VIN = VSS, VDD = 5 V 3840
1.6 1.6 0.05 0.025
4.0 mA 4.2 10 A 5
Standby operation IDD st2 [Oscillator characteristics] (Ceramic oscillator) Oscillator frequency Oscillator stabilization interval [Pull-up resistors] RPP1 I/O ports RPP2 Reset port External reset characteristic: Reset time Pin capacitance Ru tRST CP fCFOSC tCFS
4000
4160 10
kHz ms
30
70
130 k
1.0 200
2.3 500 See Figure 5.
3.9 725
f = 1 MHz, VIN = VSS for pins other than one being measured
10
pF
Note: * fCFOSC is the allowable oscillator frequency.
No. 5117-16/39
LC6529N, LC6529F, LC6529L Comparator Characteristics for Comparator Option at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter Reference input voltage range Inphase input voltage range Offset voltage Response speed Symbol VRFIN VCMIN VOFF TRS1 TRS2 IIH1 IIH2 IIL1 IIL2 RCMFB VREF0, VREF1 CMP0 to CMP3 VCMIN = VSS to VDD - 1.5 V Figure 4: VDD = 4 to 6 V Figure 4 VREF0, VREF1 CMP0 to CMP3: Without feedback resistor option VREF0, VREF1 CMP0 to CMP3: Without feedback resistor option CMP0 to CMP3: With feedback resistor option -1.0 -1.0 460 Conditions min VSS + 0.3 VSS 50 1.0 1.0 typ max VDD - 1.5 VDD - 1.5 300 5.0 200 1.0 1.0 Unit V V mV s
Input high level current
A
Input low level current Feedback resistor
A k
Table 1. Guaranteed Constants for Ceramic Oscillators
Oscillator type [External capacitor] 4-MHz ceramic oscillator 2-MHz ceramic oscillator [Built-in capacitor] 4-MHz ceramic oscillator 2-MHz ceramic oscillator Murata Kyocera Murata CS A4.00MG KBR-4.0MSA CS A2.00MG -- -- -- -- -- -- -- -- -- Kyocera -- Kyocera KBR-4.0MWS -- KBR-2.0MWS -- -- -- -- -- -- Murata Kyocera Murata Kyocera CS A4.00MG KBR-4.0MSA CS A2.00MG KBR-2.0MSA 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% -- -- -- -- Murata -- Murata -- CS AC4.00MGC 33 pF 10% 33 pF 10% -- -- -- Standard type Manufacturer Oscillator C1 C2 Rd Manufacturer Chip type Oscillator C1 C2
CS AC2.00MGC 33 pF 10% 33 pF 10% -- -- --
Figure 1 External Clock Input Waveform
No. 5117-17/39
LC6529N, LC6529F, LC6529L
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Interval
Figure 4 Comparator Response Speed (TRS) Timing
No. 5117-18/39
LC6529N, LC6529F, LC6529L
Note: When the power supply rising interval is zero, a value of 0.1 F for CRES produces a reset interval of 10 to 100 ms. If the power supply rising interval is larger, adjust CRES to produce a minimum interval of 10 ms for the oscillation to stabilize.
Figure 5 Reset Circuit
No. 5117-19/39
LC6529N, LC6529F, LC6529L LC6529L Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VI1 Input voltage VI 2 VI3 Output voltage I/O voltages Peak output current VO VIO1 VIO2 IOP IOA Average output current IOA1 IOA2 Pd max1 Allowable power dissipation Pd max2 Pd max3 Operating temperature Storage temperature Topr Tstg VDD OSC1*1 TEST, RES Port E (PE) configuration OSC2 Open-drain (OD) configuration Pull-up (PU) resistor configuration PA, PC, PD PA, PC, PD: Average for pin over 100-ms interval PA: Total current for pins PA0 to 3*2 PC, PD: Total current for pins PC0 to PC3 and PD0 to PD3*2 Ta = -40 to +85C (DIP24S) Ta = -40 to +85C (SSOP24) Ta = -40 to +85C (MFP30S) -40 -55 Conditions min -0.3 -0.3 -0.3 -0.3 typ max +7.0 VDD + 0.3 VDD + 0.3 VDD + 0.3 V V mA +15 VDD + 0.3 +20 +20 +40 +90 360 165 150 +85 +125 C mW mA V Unit V
Voltages up to that generated allowed. -0.3 -0.3 -2 -2 -6 -14
Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amplitude. 2. Averaged over 100-ms interval.
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 2.2 to 6.0 V
Parameter Supply voltage Standby voltage Symbol VDD VST VIH1 VIH2 VIH3 VIH4 VIH5 VIL1 VIL2 Input low level voltage VIL3 VIL4 VIL5 Operating frequency (cycle time) [External clock conditions] Frequency Pulse width Rise/fall times [Oscillator guaranteed constants] 2-pin RC oscillator circuit Ceramic oscillator Cext Rext OSC1, OSC2: Figure 2 OSC1, OSC2: Figure 2 Figure 3 See Table 1. 220 5% 12.0 1% pF k text textH, textL OSC1: If the clock frequency exceeds 1.040 MHz, use the built-in 1/3 or 1/4 frequency divider. Figure 1 textR, textF 200 120 100 4160 kHz ns fop (Tcyc) VDD VDD: Preserves contents of RAM and registers*. Open-drain (OD) configuration: With output N-channel transistor off Pull-up (PU) resistor configuration: With output N-channel transistor off PE: Using port E configuration RES: VDD = 1.8 to 6 V OSC1: Using external clock option PA, PC, PD: With output N-channel transistor off PE: Using port E configuration OSC1: Using external clock option TEST RES Using the built-in 1/3 or 1/4 frequency dividers extends the maximum to 4.16 MHz. Conditions min 2.2 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS 200 (20) typ max 6.0 6.0 13.5 VDD VDD VDD VDD 0.2 VDD 0.2 VDD 0.15 VDD 0.2 VDD 0.15 VDD 1040 (3.84) kHz (s) V V Unit V V
Input high level voltage
Note: * Maintain the power supply voltage at VDD until the HALT instruction has completed execution, placing the chip in the standby mode. Block chattering from entering PA3 during the HALT instruction execution cycle.
No. 5117-20/39
LC6529N, LC6529F, LC6529L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 2.2 to 6.0 V
Parameter Symbol IIH1 Input high level current IIH2 IIH3 IIL1 Conditions Open-drain (OD) configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = 13.5 V PE: Using port E configuration, VIN = VDD OSC1: Using external clock option, VIN = VDD Open-drain (OD) configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS Pull-up (PU) resistor configuration for port: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS Pull-up (PU) resistor configuration for port C: With output N-channel transistor off. (Includes transistor's leak current.) VIN = VSS PE: Using port E configuration, VIN = VSS RES: VIN = VSS OSC1: Using external clock option, VIN = VSS Pull-up (PU) resistor configuration for port C: IOH = -50 A PA, PC, PD: IOL = 3 mA PA, PC, PD: With IOL for each port less than or equal to 1 mA, IOL = 1 mA RES OSC1*: Using RC oscillator or external clock option 0.1 VDD 0.1 VDD -1.0 A -220 -71.5 min typ max 5.0 1.0 1.0 A Unit
IIL2 Input low level current IIL3 IIL4 IIL5 IIL6 Output high level voltage VOH VOL1 Output low level voltage VOL2 VHIS1 VHIS2
-6.00 -1.0 -45 -1.0 VDD - 0.5
-2.17
mA
-10
A
V 1.5 0.4 V
Hysteresis voltage
V
Note: * The RC oscillator and external clock options require a Schmidt trigger configuration for OSC1. Parameter [Current drain] RC oscillator IDD OP1 IDD OP2 IDD OP3 IDD OP4 Ceramic oscillator IDD OP5 IDD OP6 IDD OP7 IDD OP8 External clock IDD OP9 VDD: Figure 2, 400 kHz (typ) VDD: Figure 3, 4 MHz, 1/4 frequency divider VDD: Figure 3, 4 MHz, 1/4 frequency divider, VDD = 2.2 V VDD: Figure 3, 2 MHz, 1/3 frequency divider VDD: Figure 3, 2 MHz, 1/4 frequency divider VDD: Figure 3, 2 MHz, 1/3, 1/4 frequency divider VDD = 2.2 V VDD: Figure 3, 800 kHz VDD: Figure 3, 400 kHz VDD: 200 to 667 kHz, 1/1 frequency divider, 600 to 2000 kHz, 1/3 frequency divider, 800 to 2667 kHz, 1/4 frequency divider VDD: With output N-channel transistor off and port level = VDD, VDD = 6 V VDD: With output N-channel transistor off and port level = VDD, VDD = 2.2 V OSC1, OSC2: Figure 2, Cext = 220 pF 5%, Rext = 12.0 k 1% 0.4 1.6 0.4 1.3 1.3 0.3 1.1 0.9 1.0 1.0 4.0 0.8 3.0 3.0 0.6 2.6 2.4 2.5 mA mA Symbol Conditions min typ max Unit
IDD st1 Standby operation IDD st2 [Oscillator characteristics] RC oscillator Oscillator frequency fMOSC
0.05 0.025
10 A 5
275
400
577
kHz
[Oscillator characteristics] (Ceramic oscillator) OSC1, OSC2: Figure 3, fO = 400 kHz OSC1, OSC2: Figure 3, fO = 800 kHz Oscillator frequency fCFOSC* OSC1, OSC2: Figure 3, fO = 2 MHz OSC1, OSC2: Figure 3, fO = 4 MHz, 1/4 frequency divider Figure 4, fO = 400 kHz Oscillator stabilization interval tCFS Figure 4, fO = 800 kHz, fO = 2 MHz, 1/3, 1/4 frequency divider, fO = 4 MHz, 1/4 frequency divider 384 768 1920 3840 400 800 2000 4000 416 832 2080 4160 10 10 ms kHz
Continued on next page. No. 5117-21/39
LC6529N, LC6529F, LC6529L
Continued from preceding page.
Parameter [Pull-up resistors] RPP1 I/O ports RPP2 Reset port External reset characteristic: Reset time Pin capacitance Ru tRST CP f = 1 MHz, VIN = VSS for pins other than one being measured Pull-up (PU) resistor configuration for port A or D: With output N-channel transistor off and VIN = VSS, VDD = 5 V Pull-up (PU) resistor configuration for port C: With output N-channel transistor off and VIN = VSS, VDD = 5 V RES: VIN = VSS, VDD = 5 V 30 70 130 Symbol Conditions min typ max Unit
1.0 200 See Figure 6.
2.3 500
3.9 725
k
10
pF
Note * fCFOSC is the allowable oscillator frequency.
Comparator Characteristics for Comparator Option at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter Reference input voltage range Inphase input voltage range Offset voltage Response speed Input high level current Symbol VRFIN VCMIN VOFF TRS IIH1 IIH2 IIL1 IIL2 RCMFB VREF0, VREF1 CMP0 to CMP3 VCMIN = VSS to VDD - 1.5 V Figure 5 VREF0, VREF1 CMP0 to CMP3: Without feedback resistor option VREF0, VREF1 CMP0 to CMP3: Without feedback resistor option CMP0 to CMP3: With feedback resistor option -1.0 -1.0 460 Conditions min VSS + 0.3 VSS 50 1.0 typ max VDD - 1.5 VDD - 1.5 300 200 1.0 1.0 Unit V V mV s A
Input low level current Feedback resistor
A k
Table 1 Guaranteed Constants for Ceramic Oscillators
Oscillator type [External capacitor] 4-MHz ceramic oscillator 2-MHz ceramic oscillator [Built-in capacitor] 4-MHz ceramic oscillator 2-MHz ceramic oscillator 800-kHz ceramic oscillator 400-kHz ceramic oscillator Murata Kyocera Murata Murata Kyocera Murata Kyocera CS A4.00MG KBR-4.0MSA CS A2.00MG CS B800J KBR-800F/Y CS B400P KBR-400BK/Y -- -- -- -- -- -- -- -- -- Kyocera -- Kyocera -- -- -- -- KBR-4.0MWS -- KBR-2.0MWS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Murata Kyocera Murata Kyocera CS A4.00MG KBR-4.0MSA CS A2.00MG KBR-2.0MSA 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% 33 pF 10% -- -- -- -- Murata -- Murata -- CS AC4.00MGC 33 pF 10% 33 pF 10% -- -- -- Standard type Manufacturer Oscillator C1 C2 Rd Manufacturer Chip type Oscillator C1 C2
CS AC2.00MGC 33 pF 10% 33 pF 10% -- -- --
100 pF 10% 100 pF 10% 3.3 k 150 pF 10% 150 pF 10% --
220 pF 10% 220 pF 10% 3.3 k 330 pF 10% 330 pF 10% --
No. 5117-22/39
LC6529N, LC6529F, LC6529L
Figure 1 External Clock Input Waveform
Figure 2 2-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 5117-23/39
LC6529N, LC6529F, LC6529L
Figure 4 Oscillator Stabilization Interval
Figure 5 Comparator Response Speed (TRS) Timing
Note: When the power supply rising interval is zero, a value of 0.1 F for CRES produces a reset interval of 10 to 100 ms. If the power supply rising interval is larger, adjust CRES to produce a minimum interval of 10 ms for the oscillation to stabilize.
Figure 6 Reset Circuit
No. 5117-24/39
LC6529N, LC6529F, LC6529L LC6529L RC Oscillator Characteristics Figure 7 gives the RC oscillator characteristics for the LC6529L. The frequency fluctuation range is as follows: For VDD = 2.2 to 6.0 V, Ta = -40 to +85C, Cext = 220 pF, and Rext = 12.0 k, 275 kHz = fMOSC = 577 kHz These results are only guaranteed for the above RC constants. If the above values are not available, keep the RC constants within the following ranges: (See Figure 7.) Rext = 3 to 20 k, Cext = 150 to 390 pF Note: 1. The oscillator frequency must be within the range between 350 and 750 kHz for VDD = 5.0 V and Ta = 25C. 2. Make sure that the oscillator frequency remains well within the operating clock frequency range (See frequency divider option table.) for the range VDD = 2.2 to 6.0 V, Ta = -40 to +85C.
Figure 7 RC Oscillator Frequency Data (Sample Values)
No. 5117-25/39
LC6529N, LC6529F, LC6529L LC6529N/F/L Instruction Table (by Function) Abbreviations: AC: Accumulator ACt: Accumulator bit t CF: Carry flag DP: Data pointer E: E register M: Memory M (DP): Memory addressed by DP P (DPL): I/O port specified by DPL PC: Program counter
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Accumulator manipulation instructions] CLA CLC STC CMA INC DEC TAE XAE Clear AC Clear CF Set CF Complement AC Increment AC Decrement AC Transfer AC to E Exchange AC with E 1100 1110 1111 1110 0000 0000 0000 0000 0000 0001 0001 1011 1110 1111 0011 1101 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AC 0 CF 0 CF 1 AC (AC) AC (AC) + 1 AC (AC) - 1 E (AC) (AC) (E) Set AC to zero. Clear CF to zero. Set CF to one. Take ones complement of AC. ZF Add one to AC. Subtract one from AC. Copy contents of AC to E. Exchange contents of AC and E. ZF, CF ZF, CF ZF CF CF * Number of bytes Number of cycles
STACK TM: TMF: ZF: ( ), [ ]: : +: -: :
Operation
Stack register Timer Timer overflow flag Zero flag Indicates the contents of a location Transfer direction, result Addition Subtraction Exclusive or
Description Affected status bits Note
[Memory manipulation instructions] INM DEM SMB bit Increment M Decrement M Set M data bit 0010 0010 0000 1110 1111 1 0 B1 B0 1 0 B1 B0 1 1 1 1 1 1 M (DP) [M (DP)] + 1 M (DP) [M (DP)] - 1 M (DP, B1 B0) 1 M (DP, B1 B0) 0 Add one to M (DP). Subtract one from M (DP). Set bit specified by immediate data B1 B0 in M (DP) to one. Clear bit specified by immediate data B1 B0 in M (DP) to zero. ZF ZF, CF ZF, CF
RMB bit
Reset M data bit
0010
1
1
[Arithmetic, logic and comparison instructions] AD Add M to AC 0110 0000 1 1 AC (AC) + [M (DP)] AC (AC) + [M (DP)] + (CF) AC (AC) + 6 AC (AC) + 10 AC (AC) [M (DP)] Add contents of M (DP) to contents of AC and store result in AC. Add contents of M (DP) and CF to contents of AC and store result in AC. Add 6 to contents of AC. Add 10 to contents of AC. XOR contents of AC with contents of M (DP) and store result in AC. Compare contents of M (DP) with those of AC and set CF and ZF according to result. CM Compare AC with M 1111 1011 1 1 [M (DP)] + (AC) + 1 ZF, CF ZF, CF
ADC
Add M to AC with CF 0 0 1 0 Decimal adjust AC in addition Decimal adjust AC in subtraction Exclusive or M to AC
0000
1
1
ZF, CF
DAA DAS
1110 1110
0110 1010
1 1
1 1
ZF ZF
EXL
1111
0101
1
1
ZF
Note: * The second and subsequent repetitions of an LI or CLA instruction produce the same effects as an NOP instruction.
Continued on next page. No. 5117-26/39
LC6529N, LC6529F, LC6529L
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Accumulator manipulation instructions] Compare contents of immediate data field (I3 I2 I1 I0) with those of AC and set CF and ZF according to result. 2 2 I3 I2 I1 I0 + (AC) + 1 Magnitude comparison I3 I2 I1 I0 > AC I3 I2 I1 I0 = AC I3 I2 I1 I0 < AC [Load and store instructions] LI data Load AC with immediate data Store AC to M Load AC from M 1100 I3 I2 I1 I0 1 1 AC I3 I2 I1 I0 M (DP) (AC) AC [M (DP)] Load AC with contents of immediate data field (I3 I2 I1 I0). Copy contents of AC to M (DP). Copy contents of M (D) to AC. ZF ZF * ZF, CF CF ZF 0 1 1 0 1 0 Number of bytes Number of cycles Affected status bits
Operation
Description
Note
CI data
Compare AC with immediate data
0010 0100
1100 I3 I2 I1 I0
S L
0000 0010
0010 0001
1 1
1 1
[Data pointer manipulation instructions] LDZ data Load DPH with zero and DPL with immediate data respectively Load DPH with immediate data Increment DPL Decrement DPL Transfer AC to DPL Transfer DPL to AC DPH 0 DPL I3 I2 I1 I0 DPH I1 I0 DPL (DPL) + 1 DPL (DPL) - 1 DPL (AC) AC (DPL) PC P9 P8 P7 P6 P5 P 4 P 3 P 2 P1 P0 STACK (PC) + 1 PC9 to PC6, PC1, PC0 0 PC5 to PC2 P3 P2 P1 P0 STACK (PC) + 2 P9 to P0 0 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 PC (STACK) Clear DPH to zero and copy contents of immediate data field (I3 I2 I1 I0) to DPL. Copy contents of immediate data field (I1 I0) to DPH. Add one to DPL. Subtract one from DPL. Copy contents of AC to DPL. Copy contents of DPL to AC. Jump to address in immediate data field (P9 P8 P7 P6 P5 P4 P3 P2 P1 P0). ZF ZF ZF
1000
I3 I2 I1 I0
1
1
LHI data IND DED TAL TLA
0100 1110 1110 1111 1110
0 0 I1 I0 1110 1111 0111 1001
1 1 1 1 1
1 1 1 1 1
[Jump and subroutine instructions] JMP addr Jump 0 1 1 0 1 0 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 2
CZP addr
Call subroutine in the zero page
1011
P3 P2 P1 P0
1
1
Call subroutine in zero page.
CAL addr
Call subroutine
1 0 1 0 1 0 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
2
2
Call subroutine.
RT
Return from subroutine
0110
0010
1
1
Return from subroutine.
[Branch instructions] PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if ACt = 1 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if ACt = 0 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if [M (DP, t1 t0)] =1 Branch to specified address in same page (P7 to P0) if bit specified by immediate data t1 t0 in AC is one. Branch to specified address in same page (P7 to P0) if bit specified by immediate data t1 t0 in AC is zero. The mnemonic includes decimal equivalent t of immediate data i.e., BA0 to BA3. The mnemonic includes decimal equivalent t of immediate data i.e., BNA0 to BNA3. The mnemonic includes decimal equivalent t of immediate data i.e., BM0 to BM3.
BAt addr
Branch on AC bit
0 1 1 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BNAt addr
Branch on no AC bit
0 0 1 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BMt addr
Branch on M bit
0 1 1 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
Branch to specified address in same page (P7 to P0) if bit specified by immediate data t1 t0 in M (DP) is one.
Note: * The second and subsequent repetitions of an LI or CLA instruction produce the same effects as an NOP instruction.
Continued on next page. No. 5117-27/39
LC6529N, LC6529F, LC6529L
Continued from preceding page.
Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 [Branch instructions] PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if [M (DP, t1 t0)] =0 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL, t1 t0)] =1 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL, t1 t0)] =0 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if TMF = 1 then TMF 0 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if TMF = 0 then TMF 0 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if CF = 1 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if CF = 0 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if ZF = 1 PC7 to PC0 P7 P6 P5 P4 P3 P2 P1 P0 if ZF = 0 Branch to specified address in same page (P7 to P0) if bit specified by immediate data t1 t0 in M (DP) is zero. The mnemonic includes decimal equivalent t of immediate data i.e., BNM0 to BNM3. The mnemonic includes decimal equivalent t of immediate data i.e., BP0 to BP3. The mnemonic includes decimal equivalent t of immediate data i.e., BNP0 to BNP3. Number of bytes Number of cycles Affected status bits
Operation
Description
Note
BNMt addr
Branch on no M bit
0 0 1 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BPt addr
Branch on port bit
0 1 1 1 1 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
Branch to specified address in same page (P7 to P0) if bit specified by immediate data t1 t0 in P (DPL) is one. Branch to specified address in same page (P7 to P0) if bit specified by immediate data t1 t0 in P (DPL) is zero.
BNPt addr
Branch on no port bit
0 0 1 1 1 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BTM addr
Branch on timer
0111 1100 P7 P6 P5 P4 P3 P2 P1 P0
2
2
Branch to specified address in same page (P7 to P0) if TMF is one. Clear TMF to zero. Branch to specified address in same page (P7 to P0) if TMF is zero. Clear TMF to zero. Branch to specified address in same page (P7 to P0) if CF is one. Branch to specified address in same page (P7 to P0) if CF is zero. Branch to specified address in same page (P7 to P0) if ZF is one. Branch to specified address in same page (P7 to P0) if ZF is zero.
TMF
BNTM addr
Branch on no timer
0011 1100 P7 P6 P5 P4 P3 P2 P1 P0
2
2
TMF
BC addr
Branch on CF
0111 1111 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BNC addr
Branch on no CF
0011 1111 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BZ addr
Branch on ZF
0111 1110 P7 P6 P5 P4 P3 P2 P1 P0
2
2
BNZ addr
Branch on no ZF
0011 1110 P7 P6 P5 P4 P3 P2 P1 P0
2
2
[I/O instructions] IP OP Input port to AC Output AC to port 0000 0110 1100 0001 1 1 1 1 AC [P (DPL)] P (DPL) (AC) Copy contents of port specified by P (PDL) to AC. Copy contents of AC to port specified by P (DPL). Set bit specified by immediate data B1 B0 in port specified by P (DPL) to one. Clear bit specified by immediate data B1 B0 in port specified by P (DPL) to zero. Execution of this instruction invalidates contents of E. Execution of this instruction invalidates contents of E. ZF
SPB bit
Set port bit
0000
0 1 B1 B0
1
2
P (DPL, B1 B0) 1
RPB bit
Reset port bit
0010
0 1 B1 B0
1
2
P (DPL, B1 B0) 0
ZF
[Other instructions] WTTM Write timer 1111 1001 1 1 TM (E), (AC) TMF 0 Halt Copy contents of E and AC to TMF timer. Clear TMF to zero. Suspend all operations. Do nothing but consume one machine cycle. Execution requires that pin PA3 be high.
HALT
Halt
1111
0110
1
1
NOP
No operation
0000
0000
1
1
No operation
No. 5117-28/39
LC6529N, LC6529F, LC6529L The above subset excludes the following instructions from the LC6523, 6526 set AND, BFn, BI, BNFn, BNI, CLI, JPEA, OR, RAL, RCTL, RFB, TRI, RTBL, SCTL, SFB, X, XAH, XA0, XA1, XA3, XD, XH0, XH1, XI, XL0, XL1, and XM. Specifying LC6529N/F/L User Options Specifying (Ordering) LC6529N/F/L User Options When developing the software or ordering the chip, the user must prepare an EPROM containing the user program, user option data, and fixed data. There are two ways of preparing these last two: with software provided by Sanyo and manually. This Section discusses both methods. Using Sanyo's Option Specification Software SU60K, the software for specifying LC6529 options, interactively asks the user to specify the options and writes the results to a mask option file, file.OPT. The M60K macro assembler assembles the user program into an object file, file.OBJ. The L60K linker merges the mask option and object files to create an EVA file, file.EVA. The EVA2HEX conversion tool converts the user program and mask options inside the EVA file to an object file in hexadecimal (HEX) format. The user use a PROM writer to download this HEX file to the EPROM submitted when ordering the chip. For further details, see Figure A below and refer to the LC65/66K Software Manual. Alternate Method 1. Overview If not using the software for specifying LC6529 options, the user must list the mask options using the coding procedures described below and then write these with the program to the EPROM regions shown in Figure A. When ordering, the user must submit an option table list as well as the EPROM. Figure B gives an example of such a list. The procedures for coding the mask options appear on the pages following Figure B.
Figure A LC6529 ROM Data
No. 5117-29/39
LC6529N, LC6529F, LC6529L 2. Sample option table list
Figure B Sample Option Table List
No. 5117-30/39
LC6529N, LC6529F, LC6529L Coding LC6529N/L Mask Options
No. 5117-31/39
LC6529N, LC6529F, LC6529L Coding LC6529F Mask Options
No. 5117-32/39
LC6529N, LC6529F, LC6529L Using Standby HALT Mode The LC6529N/F/L features a convenient HALT mode that reduces current drain while the chip is on standby. These standby functions involve the use of one instruction (HALT) and two control signal pins (PA3 and RES). For the functions to work properly, the design of external circuits and chip software must pay due attention to these three. Depending on how extensively the standby functions are used, the designer must consider and provide countermeasures that protect the design from the effects of power supply fluctuations, power interruptions, external noise, and other adverse conditions. This document discusses the circuit and program design issues related to the most frequent application of the standby functions, the detection and recovery from power outages. When using the standby functions, follow the sample circuits given in this document and carefully observe all warnings accompanying them. Departures from the design guidelines herein will warrant thorough testing and evaluation of the effects of such sudden changes in the operating environment as momentary power outages on application operation. 1. Entering and leaving the HALT mode Table 1 gives the conditions for entering and leaving the HALT mode. Table 1 Entering and Leaving the HALT Mode
Entering HALT mode HALT instruction while PA3 is high. Leaving HALT mode 1. Reset signal (RES pin pulled low.) 2. PA3 pulled low.
Note: The second method for leaving the HALT mode is only available when the design uses an RC oscillator circuit. It may not work properly with a ceramic oscillator circuit.
2. Important notes Using the standby functions requires close attention to the following issues in application circuit and software design. * The power supply voltage must not fall below the rating while the chip is on standby. * Carefully observe all timing restrictions for the control signals during transitions to and from the HALT mode. * Make sure that a signal for leaving the HALT mode does not overlap the execution of the HALT instruction. This document demonstrates how to observe these restrictions by discussing both application circuits for a power failure recovery function and programming considerations. Such a power failure recovery function detects failure of the main power supply and causes the chip to execute a HALT instruction to put itself on standby. Reducing the current drain this way allows the backup capacitor to maintain the register contents for a longer period than otherwise possible. When the power is restored, the chip is reset and automatically resumes execution with the program counter set to 000H. The following examples discuss how the software can then distinguish this type of reset from a power on reset sequence along with issues related to dealing with momentary AC power outages. * Example 1 The first example does not distinguish a power-on reset sequence from a reset trigger by a power failure. -- Circuit diagram Figure 2-1 gives the circuit diagram for this sample circuit.
No. 5117-33/39
LC6529N, LC6529F, LC6529L
Unit (resistance: ) Note: All ports other than PA3 are configured as normal input ports.
Figure 2-1 Power Outage Backup Example 1 -- Waveforms during operation Figure 2-2 gives the waveforms relevant to the operation of the above circuit. There are three main states: (a) power-on reset sequence, (b) momentary break in main power supply, and (c) recovery from power outage backup state.
Note: V+TRON = V+ level at which transistor switches on and off
Figure 2-2 Waveforms Relevant to Operation of Circuit Example 1
No. 5117-34/39
LC6529N, LC6529F, LC6529L -- Main circuit states a: Power-on reset sequence Once the power supply voltage has reached the proper level, the chip automatically resets and begins execution with the program counter set to 000H. Caution: This circuit does not reset the chip until the power supply voltage is within the range specified for VDD, so leaves the chip in an indeterminate state. b: Momentary break in main power supply i. If only the RES pin and none of the Pxx pins drops below the threshold level VIL, the chip resets and repeats the power-on reset sequence. ii. If the RES pin and the Pxx pins remain above the threshold level VIL, the chip continues normal execution. iii. If both the RES pin and the Pxx pins drop below the threshold level VIL, the chip resets if two consecutive polls fail to detect a low at Pxx or, if a low is found, enters the HALT mode and then, because the power has been restored, leaves the HALT mode. c: Recovery from power outage backup state Since the power has been restored, the chip leaves the HALT mode. -- Design considerations a: V+ rise time and C2 The V+ rise time must be approximately ten times the RC constant for the reset circuit, C2 x R, where R is the internal resistance (typ. 200 k). It must also be no longer than approximately 20 ms. b: R1 and C1 values R1 must be as small as possible; C1, as large as possible to provide the longest backup time. At the same time, however, R1 must be large enough such that the C1 charging current does not exceed the power supply capacity. c: R2 and R3 values Choose these to make the Pxx high levels equal to VDD. d: R4 value Select R4 and thus the RC constant for C2 and R4 so that C2 discharges sometime in the interval between the point at which V+ falls below V+TRON (turning off the transistor) and the point at which Pxx falls below VIL. (Otherwise, the chip will enter the HALT mode and then not respond to a reset.) e: R5 and R6 values Select R5 and R6 so that V+ when the reset circuit operates, switching on the transistor (that is, when R5 and R6 produce a VBE of approximately 0.6 V) is at least the minimum operating voltage (VDD) plus the VF for diode D1. To provide a rapid reset once the power is restored, however, keep this voltage as small as possible while still satisfying these conditions. f: Calculating backup time From the time that the chip detects the power outage at Pxx until it executes the HALT instruction, the chip operates normally so drains relatively large amounts of current. C1 must therefore be large enough to provide backup power not only for the set's backup period, but for this transitional period as well. -- Software considerations a: Assign signals so that PA3 is maintained high during standby operation. b: The software should double-check a standby request by polling twice. Example: BP1 BP1 HALT AAA : AAA AAA : Poll once : Poll twice : Begin standby operation
No. 5117-35/39
LC6529N, LC6529F, LC6529L * Example 2 The second example distinguishes a power-on reset sequence from a reset trigger by a power failure. -- Circuit diagram Figure 2-3 gives the circuit diagram for this sample circuit.
Note: All ports other than PA3 are configured as normal input ports.
Figure 2-3 Power Outage Backup Example 2 -- Waveforms during operation Figure 2-4 gives the waveforms relevant to the operation of the above circuit. There are two main states: (a) power-on reset sequence and (b) recovery from power outage backup state.
Note: V+TRON = V+ level at which transistor switches on and off
Figure 2-4 Waveforms Relevant to Operation of Circuit Example 2
No. 5117-36/39
LC6529N, LC6529F, LC6529L -- Main circuit states a: Power-on reset sequence The operation and points to watch are the same as for the first example. The only difference is that the software interprets a low at Pxx as indicating an initial reset. b: Switch to standby operation The chip polls Pxx and, if it is low, enters the HALT mode. c: Recovery from power outage backup state Since the power has been restored, the chip leaves the HALT mode. If the recovery routine then finds that Pxx is high, it switches to a separate routine for restarting after a power outage. Caution: If the power supply voltage VDD drops below the VIH level for Pxx during the outage, this recovery routine will subsequently find that Pxx is low and execute the routine for an initial reset instead. -- Design considerations a: R2 and R3 values Make R2 much greater than R1 and choose R3 to limit TR2's IB. b: R4 value Since there are no momentary outages, the value is not critical, but select R4 so that C2 quickly discharges. In all other respects, the same considerations apply as in Example 1. -- Software considerations a: Assign signals so that PA3 is maintained high during standby operation. b: The software should check for a standby request by polling once. Example: BP1 HALT AAA : * Example 3 The third example adds support for momentary power outages. -- Circuit diagram Figure 2-5 gives the circuit diagram for this sample circuit. AAA : Poll port : Begin standby operation
Note: All ports other than PA3 are configured as normal input ports.
Figure 2-5 Power Outage Backup Example 3
No. 5117-37/39
LC6529N, LC6529F, LC6529L -- Waveforms during operation Figure 2-5 gives the waveforms relevant to the operation of the above circuit. There are three main states: (a) power-on reset sequence, (b) momentary break in main power supply, and (c) recovery from power outage backup state.
Note: V+TR1ON = V+ level at which transistor TR1 switches on and off V+TR3ON = V+ level at which transistor TR3 switches on and off
Figure 2-5 Waveforms Relevant to Operation of Circuit Example 3 -- Main circuit states a: Power-on reset sequence The operation and points to watch are the same as for the second example. b: Momentary break in main power supply i. If only the RES pin and none of the Pxx pins drops below the threshold level VIL, the chip resets. If the recovery routine then finds that Pxx is high, it switches to a separate routine for restarting after a power outage. ii. If the RES pin and the Pxx pins remain above the threshold level VIL, the chip continues normal execution. iii. If both the RES pin and the Pxx pins drop below the threshold level VIL, the chip resets if two consecutive polls fail to detect a low at Pxx or, if a low is found, enters the HALT mode and then, because the power has been restored, leaves the HALT mode. If the recovery routine then finds that Pxx is high, it switches to a separate routine for restarting after a power outage. c: Recovery from power outage backup state The operation and points to watch are the same as for the second example. -- Design considerations a: R3 value This serves as the bias resistor for transistor TR2. b: R7 and R8 values Select these so that transistor TR3 switches on and off at approximately 1.5 V. In all other respects, the same considerations apply as in Example 1. -- Software considerations The same considerations apply as in Example 1.
No. 5117-38/39
LC6529N, LC6529F, LC6529L
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1995. Specifications and information herein are subject to change without notice. PS No. 5117-39/39

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